The Reset That Erased a Two-Hundred-Millisecond Wait
Start with a measurement that exposes what a quantum computer actually spends its time doing. After a circuit runs and the answer is read out, every qubit must be pushed back to its ground state before the next program can begin. In ordinary operation that recovery takes hundreds of milliseconds. During that window the processor sits idle, a race car parked in the pits between laps.
IBM’s Nighthawk r2, released in September, attacks exactly this bottleneck with dedicated hardware. [1] Each programmable qubit gets a companion physical device whose only job is to drain its energy and return it to the ground state. Oliver Dial, a vice president of quantum systems, describes the arrangement plainly: an extra physical qubit sits on the chip beside each programmable one, and it strips the energy away fast. The gain is not marginal. IBM reports up to a 19-fold acceleration of some operations, with the recovery window collapsing from roughly 200 milliseconds to about 25 nanoseconds without disturbing neighboring qubits. [1] The arithmetic on the chip tells its own story. Nighthawk r2 carries 458 physical qubits, but only 120 of them are programmable — the rest are couplers and reset elements. The terminology bends here: these reset devices are physically identical to qubits yet cannot serve as qubits, which is why IBM sometimes calls them dissipative reset gadgets.
Two Chips, Not Nine, and the Fidelity Gap
Now the part of the plan that does not fit the earlier model. IBM’s prior roadmap promised users a single system of 1,080 qubits, assembled by chaining nine 120-qubit Nighthawk chips. That path is gone. The company now intends to deliver a 1,040-qubit machine by linking just two chips. The destination barely moved; the route was redrawn entirely.
The linking technology has been demonstrated, at least in prototype. IBM joined two Nighthawk r1 processors with four long-range couplers — L-couplers, the physical bridges that let separate processors act as one — inside the same refrigerator. State transfer fidelity reached 99.4 percent, against a long-term target of 99.9 percent. [1] Jerry Chow, IBM’s chief technology officer of quantum-centric supercomputing, says the speed of these connections is comparable to the interconnections between qubits on the chip itself.
A gap of half a percentage point sounds trivial and is not. Dial acknowledges the company is still working out how many couplers would be needed to link chips that host error-corrected qubits, though he says that question does not affect the current user-facing portion of the roadmap. IBM has also demonstrated a modular dilution refrigerator, the cryogenic plumbing that brings multiple chips and their connectors down to near-absolute-zero temperatures.
The next generation sharpens the numbers. Nighthawk r3, slated for 2027, targets 520 programmable qubits, keeping the reset architecture and adding further hardware improvements. Assuming the same ratio of programmable qubits to reset devices as in r2, that points to a chip of roughly 2,000 individual qubit-like devices — about double the largest processor IBM has offered to date. Two r3 chips joined together yield the 1,040-qubit system and support up to 10,000 operations. Jay Gambetta, director of IBM Research, frames the goal as accuracy and speed together: useful quantum computing, in his words, hinges on whether results can be delivered with both.
The Five-Chip Question That Decides the Decade
The closing measurement is not a chip. It is a count of chips. IBM’s long-term design spends roughly 300 hardware qubits to host a block of 12 logical, error-corrected qubits — the protected units that actually run algorithms. At best, one or possibly two such blocks fit on a single chip. Reaching 100-plus logical qubits, the threshold where genuinely useful algorithms become reachable, requires two things at once: a chip larger than Nighthawk r2 and five or more of those chips wired together. The revised roadmap commits IBM to both by the end of next year.
Everything else — the 19-fold reset speedup, the 99.4 percent transfer, the larger r3 chip — is preparation. The five-chip link is the voyage.
